1. Field of the Invention
The present invention relates to a semiconductor technique and, more particularly, to a technique which is especially effective when it is applied to a semiconductor integrated circuit for example, a technique which is effective when it is used in a semiconductor integrated circuit having its logic circuit composed of MIS (i.e., metal-insulator-semiconductor) elements.
2. Description of the Prior Art
Emitter-coupled logic circuits (which will hereinafter be called "ECL") are known to have the highest operating speed of all digital integrated circuits fabricated by present silicon semiconductor techniques. However, it is well known in the art that ECL circuits have a defect that their power consumption is high. A ground potential as a first power source voltage and a negative voltage (at about -5 V) as a second power source voltage are supplied to the ECL, and a digital input signal voltage having a high level beyond about -0.9 V and a low level below about -1.7 V is applied to the input terminal of the ECL so that a digital output signal voltage having a high level beyond about -0.9 V and a low level below about -1.7 V is obtained from the output terminal of the ECL. In the ECL, there are arranged a first transistor and a second transistor which have their emitters coupled, and a digital input signal voltage as above is applied to the base of the first transistor through an input terminal. A reference voltage circuit for generating a reference voltage at about -1.2 V, i.e., at an intermediate level between -0.9 V and -1.7 V is arranged in the ECL circuit, and the reference voltage is about -1.2 V is applied to the base of the second transistor. The collector of at least one of the first and second transistors is connected with a group potential through a load resistor so that the signal generated at the laod resistor is transmitted as a digital output signal voltage to the output terminal of the ECL through an emitter follower transistor.
On the other hand, a complmentary MOS (which will hereinafter be called "C-MOS") circuit, in which P-channel and N-channel MIS field effect transistors are combined, can ignore the DC current flowing through the series path of the two transistors because of the transistors is turned off when the other is turned on. Therefore, the C-MOS circuit has an advantage that its power consumption is remarkably low. Unfortunately, the C-MOS circuit has a defect that its operating speed is dependent upon the capacity of a load which is connected to the output thereof. However, the delay of the operating speed of the C-MOS can be sufficiently reduced either by having the output of the C-MOS drive a load capacitor which is formed in an integrated circuit and which has a small capacitance or by driving the load capacitor by the output of the C-MOS through a bipolar transistor.
In order to develop a novel semiconductor integrated circuit which has such signal level characteristics at its input and output terminals which are equivalent to those of the ECL and which reduces its power consumption by making use of the C-MOS, the present inventor has investigated the technique which will be described below. This novel semiconductor integrated circuit also has an advantage that, when it is to be coupled with another ECL, it is unnecessary to arrange any ECL-CMOS level conversion semiconductor integrated circuit in the coupling path.
FIGS. 1 and 2 show an example of C-MOS type semiconductor integrated circuits which have been examined by the present inventor prior to developing the preferred embodiments of the present invention on the basis of the background described above. A ground potential (GND) is supplied as a first power source voltage V.sub.CC to a terminal T.sub.1, and a negative voltage (at about -4.5 V) is supplied as a second power source voltage V.sub.EE to a terminal T.sub.2. The integrated circuit has its input terminal P.sub.in receptive of a digital input signal voltage at the ECL level so that it generates a digital output signal voltage at the ECL level at its output terminals P.sub.out. The semiconductor integrated circuit generally indicated at numeral 10 in FIGS. 1 and 2 is constructed of an internal logic circuit 20 and peripheral buffer circuits 30 and 40. Each of the circuits 20, 30 and 40 is composed of MOS type elements such as C-MOS field effect transistors.
Although not shown in FIGS. 1 and 2, the internal logic circuit 20 actually includes a number of C-MOS inverters, C-MOS NAND circuits, C-MOS NOR circuits, C-MOS flip-flops and so on so as to execute large-scale digital signal processing. Such C-MOS circuitry for logic operations are well known and a large number of logic operations can be readily performed by the circuit 20 using well-known design arrangements.
The peripheral buffer circuits 30 and 40 are exemplified by input buffer circuits 30 and output buffer circuits 40. The internal logic circuit 20 is connected through those buffer circuits 30 and 40 with the input terminal pad P.sub.in and the output terminal pad P.sub.out. The elements to be used to compose the peripheral buffer circuits 30 and 40 are MOS type elements which have sufficiently higher current capacities than those of the elements composing the internal logic circuit 20 to handle the larger current flows which occur in the buffers. As a result, the MOS type elements forming buffers 30 and 40 must be formed to have sufficiently large sizes. Instead of this, the elements composing the internal logic circuit are very small-sized so that a high integration density can be obtained.
The C-MOS type semiconductor integrated circuit of this kind consumes so little electric power that it liberates little heat. For these reasons, it is relatively easy to increase the integration density of the C-MOS type semiconductor integrated circuit of this kind. However, the inventor's studies revealed a problem with this arrangement, which will now be discussed.
Specifically, the input signal at the ECL level (which has a high level V.sub.iH of -0.9 V and a low level V.sub.iL of -1.7 V) is supplied to the input terminals P.sub.in so that the output signal at the ECL level (which has a high level V.sub.oH of -0.9 V and a low level V.sub.oL of -1.7 V) is extracted from the output terminals P.sub.out, and the negative power source voltage V.sub.EE of -4.5 V is supplied. In order to form a P-channel MOSFET F1 and an N-channel MOSFET F2 composing the internal logic circuit 20 with element areas as small as possible, it is necessary to make the ratio W/L of the width W to the length L of each channel common between the two MOSFETs F1 and F2. As a result, the logic threshold of the C-MOS inverter composed of the MOSFETs F1 and F2 is about one half (-2.25 V) of the negative power source voltage V.sub.EE.
As a result of the above requirements for the MOSFETs F1 and F2, each input buffer circuit 30 has to supply the internal logic circuit 20 with the input signal of the input terminal P.sub.in after its level has been converted, and the ratio W/L of MOSFETs F3 and F4 has to be increased to a large value for that level conversion. Considering the fanout, moreover, the output driving capacity of the input buffer circuit 30 also has to be improved. Because of this, the ON resistance R.sub.ON of the MOSFETs F3 and F4 has to be reduced to a sufficiently small value. As a result, the input buffer circuit 30 will occupy a large area in the surface of the semiconductor chip.
On the other hand, it is necessary that the output voltage of each output buffer circuit 40 be equal to or higher than the predetermined high level V.sub.oH (-0.9 V) when an output current at a predetermined level is supplied from the output terminal P.sub.out whereas the output voltage of the output buffer circuit 40 has to be equal to or lower than the predetermined low level V.sub.oL (-1.7 V) when an output current at a predetermined level is introduced from the output terminal P.sub.out. Also, it is desired that the operating speed concerning the waveform changes of the digital output signal is prevented from changing to a large extent in dependence upon the capacitance value of an external load capacitor connected with the output terminal P.sub.out. Therefore, it is necessary that the ON resistance R.sub.On of MOSFETs F5 and F6 composing the output buffer circuit 40 be set at a small value, and that the ratio W/L of the MOSFETs F5 and F6 be set at a large value. As a result, the output buffer circuit 40 also occupies a large area in the surface of the semiconductor chip.
In addition to the above problems regarding buffers 30 and 40, the gate insulating films of the C-MOS field effect transistors are liable to be broken electrostatically or by a surge voltage. As a result, in the C-MOS type semiconductor integrated circuit of FIGS. 1 and 2, it is indispensable to connect input protection circuits 32 between the peripheral buffer circuits, especially, the input buffer circuits 30 and the input terminal pad P.sub.in, as shown in FIGS. 1 and 2. However, each protection circuit 32 occupies a considerable layout area for its formation, and its RC time constant adversely affects the rise or fall of the input logic signal to cause a delay of the operating speed.